Method for fabricating a hemispherical silicon grain layer
US6124161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1998 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Dec 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.