Low power clock buffer having a reduced, clocked, pull-down transistor
US6124737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.