Semiconductor ESD protection circuit
US6125021A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1997 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An integrated circuit (10) with ESD protection is provided. The integrated circuit (10) includes a clamping device (28) connected to an input pad (12) of the integrated circuit and to ground (22). The clamping device (28) limits the peak voltage of an ESD pulse applied to the input pad (12) by conducting it to ground (22). A protection device (16) is connected to an input pad (12) of the integrated circuit (10) and to ground. The protection device (16) discharges the energy of the ESD pulse to ground. The protection device (16) is coordinated with the clamping device (28) such that the clamping device (28) turns on before the protection device (16).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.