Sector write protect CAMS for a simultaneous operation flash memory
US6125055A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simultaneous operation flash memory capable of write protecting predetermined sectors in the simultaneous operation flash memory. The preferred simultaneous operation flash memory includes a plurality of sectors divided into an upper bank and a sliding lower bank. Each bank is associated with a predetermined amount of sectors in the simultaneous operation flash memory. The simultaneous operation flash memory also includes at least one upper address decoder circuit that has a upper sector select line. During operation, each upper address decoder circuit generates a predetermined output signal on the upper sector select line when selected. In addition, the simultaneous operation flash memory includes at least one lower address decoder circuit including a lower address sector select line, wherein each upper address decoder circuit generates a predetermined output signal on the lower sector select line when selected during operation. Finally, at least one write protect CAM is electrically connected with a respective upper sector select line or a respective lower sector select line, wherein said write protect CAM generates a sector protect signal if the write protect CAM is selected b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.