Method for erasing nonvolatile memory cells in a field programmable gate array
US6125059A · kind A · utility
13Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.