Volker Hecht
29Patents
6h-index
23Co-inventors
69Inventor score
Filing activity: Jun 11, 1998 → Mar 25, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6125059A | Method for erasing nonvolatile memory cells in a field programmable gate array | Physics | 13 | Expired |
| US9704573B1 | Three-transistor resistive random access memory cells | Physics | 11 | Active |
| US6272655A | Method of reducing test time for NVM cell-based FPGA | Physics | 10 | Expired |
| US6777977B1 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Electricity | 8 | Expired |
| US6072720A | Nonvolatile reprogrammable interconnect cell with programmable buried bitline | Electricity | 8 | Expired |
| US7884640B2 | PLD providing soft wakeup logic | Electricity | 7 | Active |
| US6137728A | Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor | Electricity | 5 | Expired |
| US7212030B1 | Field programmable gate array long line routing network | Electricity | 4 | Expired |
| US7932745B2 | Inverting flip-flop for use in field programmable gate arrays | Electricity | 4 | Active |
| US7816946B1 | Inverting flip-flop for use in field programmable gate arrays | Electricity | 4 | Active |
| US8255854B2 | Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit | Physics | 2 | Active |
| US7106100B1 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Electricity | 2 | Expired |
| US9103880B2 | On-chip probe circuit for detecting faults in an FPGA | Physics | 2 | Active |
| US10147485B2 | Circuits and methods for preventing over-programming of ReRAM-based memory cells | Physics | 2 | Active |
| US7804321B2 | Circuits and methods for testing FPGA routing switches | Physics | 2 | Active |
| US7919977B2 | Circuits and methods for testing FPGA routing switches | Physics | 2 | Active |
| US9000807B2 | On-chip probe circuit for detecting faults in an FPGA | Electricity | 2 | Active |
| US10523208B2 | Efficient lookup table modules for user-programmable integrated circuits | Electricity | 2 | Active |
| US7161841B1 | Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage | Electricity | 1 | Expired |
| US7365567B2 | Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | Electricity | 1 | Active |
| US7522453B1 | Non-volatile memory with source-side column select | Physics | 1 | Active |
| US7394286B2 | Field programmable gate array long line routing network | Electricity | 1 | Active |
| US8244791B1 | Fast carry lookahead circuits | Physics | 0 | Active |
| US9990993B2 | Three-transistor resistive random access memory cells | Physics | 0 | Active |
| US11031078B2 | SEU stabilized memory cells | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.