CAS latency control circuit
US6125064A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAS latency control circuit for a SDRAM is provided for improving operation speeds of first and second CAS latencies. The circuit includes a controlling circuit unit for receiving a clock signal and providing first, second, third, and fourth control signals, a first latch for either passing or latching input data depending on the state of the first control signal, a second latch for either passing or latching the data from the first latching means depending on the state of the second control signal, a data pass selecting unit for forwarding either the data directly from the input or the data from the second latch depending on the state of the fourth control signal, and a third latch for either passing the data from the data pass selecting unit to the data output buffer or latching the data from the data pass selecting means depending on the state of the third control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.