Method of making transistors in an IC including memory cells

US6127231A · kind A · utility

Assignee

• NEC CORPORATION · JP

Inventor

• Hidemitsu Mori · Tokyo, JP

Key dates

• Filing date: Jun 17, 1998
• Grant date: Oct 3, 2000
• Expiry date: Jun 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A method of fabricating a semiconductor device using the steps of: (a) forming a large number of first transistors having a fixed gate electrode separation in a first region on a semiconductor substrate and forming a large number of second transistors having a gate electrode separation wider than that of the first transistors in a second region on the semiconductor substrate; (b) covering the entire surface of these first and second regions with an insulating film of fixed film thickness; and (c) forming a buried layer consisting of the insulating film between the gate electrodes of the first transistors by etching this entire insulating film and forming side walls consisting of the insulating film on electrodes of the second transistors. In step (c), the spaces between the gate electrodes of the first transistors are filled with insulating film in self-aligned fashion and side walls consisting of insulating film are formed on the gate electrodes of the second transistors so that the space between the gate electrodes, i.e. the diffusion layer of the first transistors, is covered with insulating film and is not exposed to the etching atmosphere.