Porous region removing method and semiconductor substrate manufacturing method
US6127281A · kind A · utility
11Cited by
1References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention is to ensure a high planarity of an underlying layer after a porous layer is removed. A substrate to be processed is dipped in an etchant. In the first step, pores in the porous Si layer are filled with the etchant by supplying an ultrasonic wave. In the second step, supply of the ultrasonic wave is stopped, and the pore walls are thinned by the etching function. In the third step, the ultrasonic wave is supplied again to break the porous layer at once.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.