Semiconductor device having an SOI structure and manufacturing method therefor
US6127702A · kind A · utility
527Cited by
4References
35Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 16, 1997 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Sep 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.