Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region
US6127703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/105
Abstract
A lateral thin-film Silicon-On-Insulator (SOI) PMOS device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral PMOS transistor device in an SOI layer on the buried insulating layer and having a source region of p-type conductivity formed in a body region of n-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of p-type conductivity is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region. In order to simply and economically implement the PMOS transistor device, the lateral drift region is provided with a linearly-graded charge profile over at least a major portion of its lateral extent and a surface-adjoining p-type conductivity drain extension region is provided in the drift region and extends from the drain region to adjacent to, but not in direct contact with,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.