Heterojunction bipolar transistor and manufacturing method thereof

US6127716A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kouhei Morizuka · Yokohama, JP
• Masayuki Sugiura · Yokohama, JP

Key dates

• Filing date: Oct 8, 1999
• Grant date: Oct 3, 2000
• Expiry date: Oct 8, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/821

Abstract

On an n-type semiconductor substrate 41 doped in high density, a p-type semiconductor layer 2, an n-type semiconductor layer 4 doped in high density, which is a collector, a p-type semiconductor layer 6 doped in high density, which is a base, and the n-type semiconductor layer 7, which is an emitter, are sequentially stacked. To the collector layer, a collector electrode 12 is electrically connected, and to the base layer, a base electrode 11 is electrically connected, and to the emitter layer, an emitter electrode 9 is electrically connected, and thus a bipolar transistor is structured. On the bipolar transistor, an insulated isolation area 55 is formed with an opening therein, whose depth reaches the surface of the substrate, and a substrate electrode 48 is formed thereon. On the bipolar transistor and the insulated isolation area 55, an inter-layer dielectric layer 54 is formed having contact holes formed to upper parts of the emitter electrode 49 and to the substrate electrode 48. The emitter electrode 49 and the substrate electrode 48 are connected to each other by ground wiring.