IDDQ testable programmable logic arrays
US6127838A · kind A · utility
5Cited by
7References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 3, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Mar 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.