Low power clock buffer with shared, clocked transistor
US6127850A · kind A · utility
4Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.