Method and circuit for reading low-supply-voltage nonvolatile memory cells
US6128225A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor interposed between the supply line and the reference cell; and the array and reference load transistors form a current mirror wherein the array load transistor is diode-connected and presents a first predetermined channel width/length ratio, and the reference load transistor presents a second predetermined channel width/length ratio N times greater than the first ratio, so that the current flowing in the array cell is supplied, amplified, to the reference branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.