Integrated processor/memory device with victim data cache
US6128702A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1999 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Jan 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank. When the CPU issues an address in the portion of the address space of the corresponding main memory bank, the corresponding primary cache bank determines whether a cache hit or a cache miss has occurred. When a cache miss occurs, the primary cache bank replaces a victim cache line of the cache lines in the primary cache bank with a ne…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.