Apparatus and method for a load bias--load with intent to semaphore
US6128706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1998 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Feb 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.