Continuously powered mainstore for large memory subsystems
US6128746A · kind A · utility
104Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1997 |
| Grant date | Oct 3, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.