Inventor · Rochester, MN, US

Joseph A. Kirscht

68Patents
8h-index
37Co-inventors
78Inventor score

Filing activity: Aug 26, 1997 → Nov 21, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US6128746A Continuously powered mainstore for large memory subsystems Emerging Cross-Sectional Technologies 104 Expired
US7984357B2 Implementing minimized latency and maximized reliability when data traverses multiple buses Physics 17 Active
US7882323B2 Scheduling of background scrub commands to reduce high workload memory request latency Physics 14 Active
US7010654B2 Methods and systems for re-ordering commands to access memory Physics 13 Expired
US7908443B2 Memory controller and method for optimized read/modify/write performance Physics 11 Active
US7328315B2 System and method for managing mirrored memory transactions and error recovery Physics 11 Expired
US8140937B2 Memory initialization time reduction Physics 9 Active
US7925857B2 Method for increasing cache directory associativity classes via efficient tag bit reclaimation Physics 9 Active
US8082396B2 Selecting a command to send to memory Physics 6 Active
US7290185B2 Methods and apparatus for reducing memory errors Physics 6 Expired
US7882314B2 Efficient scheduling of background scrub commands Physics 6 Active
US7328317B2 Memory controller and method for optimized read/modify/write performance Physics 6 Expired
US7987336B2 Reducing power-on time by simulating operating system memory hot add Physics 5 Active
US8549217B2 Spacing periodic commands to a volatile memory for increased performance and decreased collision Physics 5 Active
US7761669B2 Memory controller granular read queue dynamic optimization of command selection Physics 4 Active
US6963516B2 Dynamic optimization of latency and bandwidth on DRAM interfaces Physics 4 Expired
US7650259B2 Method for tuning chipset parameters to achieve optimal performance under varying workload types Physics 4 Active
US9213595B2 Handling errors in ternary content addressable memories Physics 3 Active
US8028128B2 Method for increasing cache directory associativity classes in a system with a register space memory Physics 3 Active
US8572455B2 Systems and methods to respond to error detection Physics 3 Active
US7970980B2 Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures Physics 3 Active
US8103930B2 Apparatus for implementing processor bus speculative data completion Physics 3 Active
US9473502B2 Atomically updating ternary content addressable memory-based access control lists Physics 3 Active
US8397100B2 Managing memory refreshes Physics 3 Active
US7516270B2 Memory controller and method for scrubbing memory without using explicit atomic operations Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.