Method of making self-aligned stacked gate flush memory with high control gate to floating gate coupling ratio
US6130129A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1998 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Jul 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
An improved process for fabricating flash memory cells with high control-gate-to-floating-gate coupling ratio is disclosed. The flash memory cell contains: (a) a substrate; (b) at least a pair of spaced-apart floating gates on the substrate, each of the floating gate has a pair of poly sidewall spacers; (c) a field oxide layer (FOX) partially recessed into the substrate; (d) an oxide/nitride/oxide (ONO) layer covering each of the floating gates; (e) a control gate covering the oxide/nitride/oxide layer and the field oxide layer. The design of the flash memory cell allows the field oxide layer to be wedged between the pair of floating gates and below the poly sidewall spacers. The poly sidewall spacers substantially increases the overlapping area between the control gate and the floating gate, thus allowing the control-gate-to-floating-gate coupling ratio and the performance of the flash memory to be enhanced. Also, since the field oxide layer and the floating gates are self-aligned, high density flash memory can be made from this process. Furthermore, the distance between the floating gates can be shorter than that limited by the underlying photolithography technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.