Thin film transistor matrix device
US6130456A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1997 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Oct 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6729
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.