Electrically alterable antifuse using FET
US6130469A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.