Ballasting of high power silicon-germanium heterojunction biploar transistors
US6130471A · kind A · utility
9Cited by
18References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/125
Abstract
A ballasted transistor structure reduces thermal runaway. A heterojunction bipolar junction transistor array includes a plurality of transistors, each having an emitter, a base and a collector. Each of the bases is an alloy of silicon and germanium and each of the collectors and emitters is silicon. A ballast resistor, of doped silicon, that prevents thermal runaway, is electrically connected to each of the collectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.