Processing high-speed digital datastreams with reduced memory
US6131151A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for managing high-bandwidth incoming digital data streams, such as MPEG encoded data streams, while reducing memory requirements. Frames of incoming data are divided into smaller slices, for example four slices per frame. A sequencing memory is used to store frame store memory addresses pointing to locations in the frame store buffer where slices of data are stored. As incoming data is stored in the frame buffer, corresponding start location addresses are stored in the sequencing memory, and corresponding bits in a status register are marked as busy. Conversely, as data is read out of the frame store for decoding or reconstruction, the corresponding bit in the status register is changed to the free status, as each slice of data is processed. This procedure and corresponding architecture reduces frame store memory requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.