Method of implementation of MOS transistor gates with a high content
US6132806A · kind A · utility
17Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0<y<30%; and depositing an Si.sub.1-z Ge.sub.z layer of desired thickness, where z>50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.