Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement
US6133106A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOSFET includes: depositing an oxide layer on the planarized substrate; forming a silicon nitride island above a gate region in the substrate; building an oxide sidewall about the nitride island; forming a source region and a drain region in the substrate; removing the silicon nitride island, thereby leaving a void over the gate region; forming a gate dielectric over the gate region in the void; filling the void and the areas over the source region and drain region; planarizing the upper surface of the structure by chemical mechanical polishing; depositing a metal layer on the upper surface of the structure; and metallizing the structure to form electrodes in electrical contact with the source region, the gate region, and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.