Method for fabricating a shallow trench isolation
US6133114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Sep 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.