Three dimensional packaging configuration for multi-chip module assembly
US6133626A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip module (MCM) assembly has three stacked integrated circuit (IC) layers. The first IC layer is electrically flip-chip connected to a substrate. The back of the second IC layer may be glued to the back of the first IC layer, and the second and third IC layers are electrically flip-chip connected to each other. In one embodiment, the third IC layer is electrically connected to the substrate through a vertical interconnect element for high circuit density. In another, the second IC layer is electrically connected to the substrate using wire bonding for greater post-fabrication customization flexibility. In still another embodiment, the MCM assembly comprises two stacked IC layers where the second IC layer is electrically flip-chip connected to the first IC layer and the second layer is electrically connected to the substrate through a vertical interconnect element. By directly connecting IC layers, higher circuit density, lower trace impedance, and lower cross-talk or electrical noise susceptibility is achieved over that presently offered by most current MCM assemblies. The assembly accommodates different sized IC layers, multiple ICs on each layer, and different technolog…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.