Method and apparatus for reducing high current during chip erase in flash memories
US6134149A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Mar 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a V.sub.CC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the V.sub.CC power supply to ensure the memory cell array is properly erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.