Patent · US Expired

Memory controller supporting DRAM circuits with different operating speeds

US6134638A · kind A · utility

187Cited by

7References

37Claims

0Family size

Assignee

Compaq Computer Corporation · US

Inventors

S. Paul Olarig · Cypress, US
Christopher J. Pettey · Cedar Park, US

Key dates

Filing date	Aug 13, 1997
Grant date	Oct 17, 2000
Priority date	—
Expiry date	Aug 13, 2017

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1694
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.