Method of and system for allowing a computer system to access cacheable memory in a non-cacheable manner
US6134641A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Mar 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and a system for allowing cacheable system memory to be accessed in a non-cacheable manner. In one embodiment of the present invention, a computer system is tricked during POST (Power-On Self-Test) to reserve a first region in a non-cacheable address space for a virtual peripheral device. The computer system is then tricked during operating system startup to reserve a second region in a cacheable address space. In the present embodiment, the first region is then mapped to the second region such that accesses to the first region is automatically forwarded to the second region. As a result, objectives of the present invention are achieved as cacheable memory may be accessed via accessing non-cacheable memory of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.