System and method for executing and completing store instructions
US6134646A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Jul 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.