Package parallel test method and apparatus
US6134685A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2893
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for partial parallel testing a plurality of integrated circuit packages using a multi-package tester head having a plurality of sockets. Each socket is used for testing an integrated circuit package. A first one of the sockets has a full complement of signal channels, and the other sockets have exclusive subsets of the full complement of signal channels. The first socket and the other sockets support parallel testing of the integrated circuit packages according to a first type of test. Only the first socket, with its full complement of signal channels, supports a second type of test. To test a plurality of integrated circuit packages, a group of packages are inserted in the sockets. A first-pass test is then performed, in parallel, on the packages in the sockets. Then, for packages that passed the first-pass test, second-pass testing is performed sequentially using the first socket.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.