Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit

US6136640A · kind A · utility

Assignee

• STMicroelectronics SA

Inventors

• Michel Marty · Buc, FR
• Harve Jaouen · Meylan, FR

Key dates

• Filing date: Jul 17, 1998
• Grant date: Oct 24, 2000
• Expiry date: Jul 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/68

Abstract

A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the lower insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.