Method for manufacturing DRAM capacitor
US6136646A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings. A conformal conductive layer that covers the exposed surfaces of the electrode openings and the node contact openings are formed, hence forming the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode, and finally an upper electrode is formed over the dielectric layer to form a complete capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.