Stacked capacitator memory cell and method of fabrication

US6136660A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Hua Shen · Beacon, US
• Gerhard Kunkel · Radebeul, DE
• Martin Gutsche · Dorfen, DE

Key dates

• Filing date: Sep 28, 1998
• Grant date: Oct 24, 2000
• Expiry date: Sep 28, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0335

Abstract

A memory cell includes a field effect transistor and a stacked capacitor. The stacked capacitor has one plate formed by a platinum layer over the side walls of a portion of a dielectric layer that overlies a conductive layer that makes contact to a conductive plug connected to the storage node of the cell. The capacitor dielectric overlies the sidewalls and top of the dielectric layer portion and the other plate of the capacitor is formed by a platinum layer over the capacitor dielectric.