Self-aligned dual thickness cobalt silicide layer formation process
US6136705A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Oct 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques. Cobalt from the cobalt layer is subsequently reacted with silicon from the exposed silicon substrate surfaces to form a first self-aligned cobalt silicide layer on these surfaces. At the same time, cobalt from the cobalt layer is reacted with silicon from the silicon l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.