Integrated SCR-LDMOS power device
US6137140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/403
Abstract
An integrated SCR-LDMOS device (10) having a p+ region (13) in the drain region (12), but otherwise similar to a conventional LDMOS transistor. The device (10) may be implemented as a modification of a non-planar LDMOS (FIGS. 1 and 2). An alternate embodiment, device (30), may be implemented as a modification of a planar LDMOS (FIG. 3). In either case, the added p+ region (13, 37) provides the device (10, 30) with two parasitic bipolar transistors in an SCR configuration (FIGS. 4A and 4B).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.