Planarized deep-shallow trench isolation for CMOS/bipolar devices
US6137152A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.