Planar guard ring
US6137155A · kind A · utility
32Cited by
12References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.