Thin stacked integrated circuit device
US6137164A · kind A · utility
209Cited by
15References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.