FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication

US6140171A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Archibald J. Allen · Shelburne, US
• Jerome B. Lasky · South Burlington, US
• Randy W. Mann · Jericho, US
• John J. Pekarik · Underhill, US
• Jed H. Rankin · South Burlington, US
• Edward W. Sengle · South Burlington, US
• Francis R. White · Saint Johnsbury Center, US

Key dates

• Filing date: Jan 20, 1999
• Grant date: Oct 31, 2000
• Expiry date: Jan 20, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.