Post etch silicide formation using dielectric etchback after global planarization
US6140216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.