Semiconductor memory device and fabricating method
US6140673A · kind A · utility
18Cited by
7References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In a high-integration DRAM device using a SOI substrate, a conductive film for connecting the source region or the drain region to the polysilicon film filled in the trench is formed in an etched-off portion of the insulating layer of the SOI substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.