Method of utilizing IDDQ tests to screen out defective parts
US6140832A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Jun 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.