Refresh control circuit
US6141279A · kind A · utility
10Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh control circuit is provided that includes a control signal latency setting circuit that sets a control signal (CAS) latency, and a refresh mode setting that receives an output signal (REF) from the auto refresh mode decoder and an output signal (SREF) from the self-refresh mode decoder and outputs an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.