Method and apparatus for an improved reset and power-on arrangement for DRAM generator controller
US6141284A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.