Technique for detecting memory part failures and single, double, and triple bit errors
US6141789A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.