Commonly housed diverse semiconductor die with reduced inductance
US6144093A · kind A · utility
55Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Apr 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET die and a Schottky diode die are each mounted within a device package on a common lead frame pad with their drain and cathode terminals, respectively, connected together at the common pad. The source terminal of the MOS gated device and the anode terminal of the Schottky diode are each electrically connected by wire bonds to an insulated pin, and the gate electrode of the MOS gated device is electrically connected by wire bonds to another pin. A redundant wire connection runs from the source terminal of the MOS gated device to the anode terminal of the Schottky diode reduce the inductance in the anode lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.