Graded PB for C4 bump technology
US6144103A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1999 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Aug 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3463
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved solder bump composition and method advantageously employs a thin low-alpha layer of lead (Pb) deposited in close proximity to alpha particle sensitive devices, while ordinary (i.e., low cost) Pb is used for the bulk of the solder bump. This approach allows for reduced overall cost while still providing protection from alpha-particle induced soft errors. The low-alpha layer reduces the flux of alpha particle into devices in two ways. First, the low-alpha layer is itself essentially Pb.sup.210 free and therefore alpha particle emissions from the low-alpha layer are negligible. Second, the low-alpha layer is substantially opaque to alpha particles emitted by the ordinary Pb which includes Pb.sup.210. As a result, sensitive circuits on a semiconductor chip employing the improved solder bump are shielded from alpha particle emissions of the low-cost Pb.sup.210 -containing portion of a solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.